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74AUP1G17 Datasheet

Part Number 74AUP1G17
Manufacturers NXP
Logo NXP
Description Low-power Schmitt-trigger buffer
Datasheet 74AUP1G17 Datasheet74AUP1G17 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G17 Low-power Schmitt-trigger buffer Rev. 01 — 26 July 2005 Product data sheet 1. General description The 74AUP1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the enti.

  74AUP1G17   74AUP1G17






Part Number 74AUP1G17
Manufacturers Diodes
Logo Diodes
Description SINGLE SCHMITT-TRIGGER BUFFER
Datasheet 74AUP1G17 Datasheet74AUP1G17 Datasheet (PDF)

74AUP1G17 SINGLE SCHMITT-TRIGGER BUFFER Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current bac.

  74AUP1G17   74AUP1G17







Part Number 74AUP1G17
Manufacturers nexperia
Logo nexperia
Description Low-power Schmitt trigger
Datasheet 74AUP1G17 Datasheet74AUP1G17 Datasheet (PDF)

74AUP1G17 Low-power Schmitt trigger Rev. 13 — 13 January 2022 Product data sheet 1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2..

  74AUP1G17   74AUP1G17







Low-power Schmitt-trigger buffer

www.DataSheet4U.com 74AUP1G17 Low-power Schmitt-trigger buffer Rev. 01 — 26 July 2005 Product data sheet 1. General description The 74AUP1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry pr.


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