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74AUP1G18 Datasheet

Part Number 74AUP1G18
Manufacturers nexperia
Logo nexperia
Description Low-power 1-of-2 demultiplexer
Datasheet 74AUP1G18 Datasheet74AUP1G18 Datasheet (PDF)

74AUP1G18 Low-power 1-of-2 demultiplexer with 3-state deselected output Rev. 7 — 18 January 2022 Product data sheet 1. General description The 74AUP1G18 is a 1-to-2 demultiplexer with a 3-state outputs. The device buffers the data on input A and passes it to output 1Y or 2Y, depending on whether the state of the select input (S) is LOW or HIGH. The unused output assumes the high impedence OFF-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fal.

  74AUP1G18   74AUP1G18






Part Number 74AUP1G19
Manufacturers nexperia
Logo nexperia
Description Low-power 1-of-2 decoder/demultiplexer
Datasheet 74AUP1G18 Datasheet74AUP1G19 Datasheet (PDF)

74AUP1G19 Low-power 1-of-2 decoder/demultiplexer Rev. 7 — 19 January 2022 Product data sheet 1. General description The 74AUP1G19 is a 1-to-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH E causes both outputs to assume a HIGH state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device.

  74AUP1G18   74AUP1G18







Part Number 74AUP1G175-Q100
Manufacturers nexperia
Logo nexperia
Description Low-power D-type flip-flop
Datasheet 74AUP1G18 Datasheet74AUP1G175-Q100 Datasheet (PDF)

74AUP1G175-Q100 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 4 — 18 January 2022 Product data sheet 1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be.

  74AUP1G18   74AUP1G18







Part Number 74AUP1G175
Manufacturers nexperia
Logo nexperia
Description Low-power D-type flip-flop
Datasheet 74AUP1G18 Datasheet74AUP1G175 Datasheet (PDF)

74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 7 — 18 January 2022 Product data sheet 1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be rese.

  74AUP1G18   74AUP1G18







Part Number 74AUP1G175
Manufacturers NXP
Logo NXP
Description Low Power D-Type Flip-Flop
Datasheet 74AUP1G18 Datasheet74AUP1G175 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 01 — 15 November 2006 Product data sheet 1. General description The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic p.

  74AUP1G18   74AUP1G18







Low-power 1-of-2 demultiplexer

74AUP1G18 Low-power 1-of-2 demultiplexer with 3-state deselected output Rev. 7 — 18 January 2022 Product data sheet 1. General description The 74AUP1G18 is a 1-to-2 demultiplexer with a 3-state outputs. The device buffers the data on input A and passes it to output 1Y or 2Y, depending on whether the state of the select input (S) is LOW or HIGH. The unused output assumes the high impedence OFF-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F Class 3A exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Low static power consumption; ICC = 0.9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD 78 Class II • Overvoltage tolerant inputs to 3.6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial.


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