74AUP1T50

74AUP1T50 Low-power buffer with voltage-level translator Rev. 4 — 5 August 2022 Product data sheet 1. General description The 74AUP1T50 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T50 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range. 2. Features and benefits Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 1.5 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Pac...