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74AUP2G08 Datasheet

Part Number 74AUP2G08
Manufacturers nexperia
Logo nexperia
Description Low-power dual 2-input AND gate
Datasheet 74AUP2G08 Datasheet74AUP2G08 Datasheet (PDF)

74AUP2G08 Low-power dual 2-input AND gate Rev. 11 — 17 June 2022 Product data sheet 1. General description The 74AUP2G08 is a dual 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the.

  74AUP2G08   74AUP2G08






Part Number 74AUP2G08
Manufacturers NXP
Logo NXP
Description Low Power Dual 2-Input AND Gate
Datasheet 74AUP2G08 Datasheet74AUP2G08 Datasheet (PDF)

74AUP2G08 Low-power dual 2-input AND gate Rev. 7 — 18 January 2013 Product data sheet 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications us.

  74AUP2G08   74AUP2G08







Part Number 74AUP2G08
Manufacturers Diodes
Logo Diodes
Description DUAL AND GATE
Datasheet 74AUP2G08 Datasheet74AUP2G08 Datasheet (PDF)

NEW PRODUCT 74AUP2G08 DUAL AND GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G08 is a dual two input AND gate. Both gates have push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow whe.

  74AUP2G08   74AUP2G08







Low-power dual 2-input AND gate

74AUP2G08 Low-power dual 2-input AND gate Rev. 11 — 17 June 2022 Product data sheet 1. General description The 74AUP2G08 is a dual 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • CMOS low power dissipation • Low static power consumption; ICC = 0.9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD78 Class II • Overvoltage tolerant inputs to 3.6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F Class 3A exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C Nexperia 74AUP2G08 Low-power dual 2-input AND gate 3. Ordering information T.


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