74HC164-Q100

74HC164-Q100; 74HCT164-Q100 8-bit serial-in, parallel-out shift register Rev. 2 — 11 June 2020 Product data sheet 1. General description The 74HC164-Q100; 74HCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC164-Q100: CMOS level For 74HCT164-Q100: TTL level Gated serial data inputs Asynchronous master reset Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B ESD protection: MIL-STD-883, ...