74HC4017 Datasheet PDF
decade counter
- 74HC4017 | NXP
- Johnson decade counter
-
.
- 74HC4017 | Texas Instruments
- Decade Counter/Divider
-
CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor SCHS200D
High-Speed CMOS Logic
November 1997 - Revised October 2003 Decade Counter/Divider with 10 Decoded Outputs
[ /Title (CD74 HC401 7) /Subject (High Speed CMOS Logic Decade Counte
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature R.
- 74HC4017 | nexperia
- Johnson decade counter
-
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 7 — 10 May 2021
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is .
- 74HC4017 | Texas Instruments
- Decade Counter/Divider
- CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor SCHS200D
High-Speed CMOS Logi.
- CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor SCHS200D
High-Speed CMOS Logic
November 1997 - Revised October 2003 Decade Counter/Divider with 10 Decoded Outputs
[ /Title (CD74 HC401 7) /Subject (High Speed CMOS Logic Decade Counte
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature R.
- 74HC4017 | nexperia
- Johnson decade counter
- 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 7 — 10 May 2021
Product d.
- 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 7 — 10 May 2021
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is .
- 74HC4017 | NXP
- Johnson decade counter
- .
- .
- 74HC4017-Q100 | nexperia
- Johnson decade counter
- 74HC4017-Q100;
74HCT4017-Q100
Johnson decade counter with 10 decoded outputs
Rev. 2 — 1 July 2020.
- 74HC4017-Q100;
74HCT4017-Q100
Johnson decade counter with 10 decoded outputs
Rev. 2 — 1 July 2020
Product data sheet
1. General description
The 74HC4017-Q100; 74HCT4017-Q100 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition.
- 74HC4017BQ | nexperia
- Johnson decade counter
- 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 7 — 10 May 2021
Product d.
- 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 7 — 10 May 2021
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is .
2016-06-01 : 74HC4075-Q100 UCC2808-1 74HC4094 74HC4020 74HCT9046A 74HC4051 74HCT4051 74HC4017 74HC40105 74HC4002