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74HC574 Flip-Flop Datasheet PDFOctal 3-State Noninverting D Flip-Flop Octal 3-State Noninverting D Flip-Flop |
　
　
　
| Part Number | 74HC574 |
|---|---|
| Description | Octal 3-State Noninverting D Flip-Flop |
| Feature | 74HC574 Octal 3−State Noninverting D F lip−Flop
High−Performance Silicon∠’Gate CMOS
The 74HC574 is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outpu ts; with pull−up resistors, they are compatible with LSTTL outputs. Data mee ting the set−up time is clocked to th e outputs with the rising edge of the C lock. The Output Enable input does not affect the states of the flip−flops b ut when Output Enable is high, all devi ce outputs are forced to the high−imp edance state. Thus, data may be stored even when the outputs are not enabled. The HC574 is identical in func . |
| Manufacture | ON Semiconductor |
| Datasheet |
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| Part Number | 74HC574 |
|---|---|
| Description | Octal D-type flip-flop |
| Feature | 74HC574; 74HCT574
Octal D-type flip-flo p; positive edge-trigger; 3-state
Rev. 7 — 4 March 2016 Product data sheet 1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge trig gered D-type flip-flop with 3-state out puts. The device features a clock (CP) and output enable (OE) inputs. The flip -flops will store the state of their in dividual D-inputs that meet the set-up and hold time requirements on the LOW-t o-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high -impedance OFF-state. Operation of the OE input does not affect the state of t he flip-flops. I . |
| Manufacture | NXP |
| Datasheet |
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| Part Number | 74HC574 |
|---|---|
| Description | Octal D-type flip-flop |
| Feature | 74HC574; 74HCT574
Octal D-type flip-flo p; positive edge-trigger; 3-state
Rev. 8 — 30 July 2021 Product data sheet 1. General description The 74HC574; 7 4HCT574 is an 8-bit positive-edge trigg ered D-type flip-flop with 3-state outp uts. The device features a clock (CP) a nd output enable (OE) inputs. The flip- flops will store the state of their ind ividual D-inputs that meet the set-up a nd hold time requirements on the LOW-to -HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high- impedance OFF-state. Operation of the O E input does not affect the state of th e flip-flops. In . |
| Manufacture | nexperia |
| Datasheet |
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