74HC595A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High–Performance Silicon–Gate CMOS The MC54/74HC595A is identical in pinout to the LS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 — Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity SERIAL DATA INPUT A 14 LOGIC DIAGRAM SHIFT REGISTER LATCH SHIFT 11 CLOCK RESET 10 LATCH 12 CLOCK OUTPUT 13 ENABLE VCC = PIN 16 GND = PIN 8 15 QA 1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH PARALLEL DATA OUTPUTS 9 SQH SERIAL DAT...