register. 74HC595D Datasheet

74HC595D Datasheet PDF

Part 74HC595D
Description serial or parallel-out shift register
Feature 74HC595D; 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-sta.
Manufacture nexperia
Datasheet
Download 74HC595D Datasheet

74HC595; 74HCT595 8-bit serial-in, serial or parallel-out s 74HC595D Datasheet
74HC595; 74HCT595 8-bit serial-in, serial or parallel-out s 74HC595DB Datasheet





74HC595D
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 9 — 28 February 2017
Product data sheet
1 General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an asynchronous reset MR input. A LOW on MR will reset the shift
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of
the STCP input. If both clocks are connected together, the shift register will always be
one clock pulse ahead of the storage register. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the
outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the registers. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2 Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3 Applications
Serial-to-parallel data conversion
Remote control holding register



74HC595D
Nexperia
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4 Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
74HC595D
-40 °C to +125 °C
74HCT595D
74HC595DB -40 °C to +125 °C
74HCT595DB
74HC595PW -40 °C to +125 °C
74HCT595PW
74HC595BQ -40 °C to +125 °C
74HCT595BQ
Name
Description
Version
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16
plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5 Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S 9
12 STCP
8-BIT STORAGE REGISTER
Figure 1. Functional diagram
13 OE
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1 2 3 4 5 6 7 mna554
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
2 / 22



74HC595D
Nexperia
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
11 12
SHCP STCP
14
DS
Q7S 9
Q0 15
Q1 1
Q2 2
Q3 3
Q4 4
Q5 5
Q6 6
Q7 7
MR OE
10 13
mna552
Figure 2. Logic symbol
DS
SHCP
MR
STAGE 0
DQ
FF0
CP
R
13
EN3
12
C2
10 R
SRG8
11
C1/
14 1D
2D
3
15
1
2
3
4
5
6
7
9
Figure 3. IEC logic symbol
mna553
STAGES 1 TO 6
STAGE 7
D
Q
DQ
Q7S
FF7
CP
R
STCP
OE
DQ
LATCH
CP
DQ
LATCH
CP
Figure 4. Logic diagram
Q0
Q1 Q2 Q3 Q4 Q5 Q6
mna555
Q7
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
3 / 22






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