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74HCT257 Multiplexer Datasheet PDFHigh-Speed CMOS Logic Quad 2-Input Multiplexer High-Speed CMOS Logic Quad 2-Input Multiplexer |
Part Number | 74HCT257 |
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Description | High-Speed CMOS Logic Quad 2-Input Multiplexer |
Feature | Data sheet acquired from Harris Semicond uctor SCHS171D
November 1997 - Revised October 2003
CD54HC257, CD74HC257, CD5 4HCT257, CD74HCT257
High-Speed CMOS Log ic Quad 2-Input Multiplexer with Three- State Non-Inverting Outputs
[ /Title ( CD74 HC257 , CD74 HCT25 7) /Subject (Hi gh Speed CMOS Logic Quad 2-Input Multip lexer
Features
• Buffered Inputs • Typical Propagation Delay ( In to Outp ut ) = 12ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Ran ge) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driv er Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide . |
Manufacture | Texas Instruments |
Datasheet |
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Part Number | 74HCT257 |
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Description | Quad 2-input multiplexer |
Feature | INTEGRATED CIRCUITS
DATA SHEET
For a com plete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC /HCT/HCU/HCMOS Logic Package Informatio n • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT257 Quad 2-i nput multiplexer; 3-state Product spec ification Supersedes data of September 1993 File under Integrated Circuits, I C06 1998 Sep 30 Philips Semiconductor s Quad 2-input multiplexer; 3-state Pr oduct specification 74HC/HCT257 FEATU RES • Non-inverting data path • 3-s tate outputs interface directly with sy stem bus • Output capability . |
Manufacture | Philips |
Datasheet |
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Part Number | 74HCT257 |
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Description | Quad 2-input multiplexer |
Feature | 74HC257; 74HCT257
Quad 2-input multiplex er; 3-state
Rev. 8 — 9 February 2021 Product data sheet 1. General descrip tion The 74HC257; 74HCT257 is a quad 2- input multiplexer with 3-state outputs. Inputs include clamp diodes. This enab les the use of current limiting resisto rs to interface inputs to voltages in e xcess of VCC. 2. Features and benefits • Wide supply voltage range from 2. 0 V to 6. 0 V • CMOS low power dissipat ion • High noise immunity • Latch-u p performance exceeds 100 mA per JESD 7 8 Class II Level B • Complies with JE DEC standards: • JESD8C (2. 7 V to 3. 6 V) • JESD7A (2. 0 V to 6. 0 V . |
Manufacture | nexperia |
Datasheet |
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