74HCT273

74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 5 — 26 February 2016 Product data sheet 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Input levels:  For 74HC273: CMOS level  For 74HCT273: TTL level  Common clock and master reset  Eight positive edge-triggered D-type flip-flops  Complies with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC273D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74HCT273D 74HC273DB 40 C to +125 C SSOP20 74HCT273DB plastic shrink small outline package; 20 leads; body width SOT339-1 5.3 mm 74HC273PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body 74HCT273P...