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74HCT374 flip-flop Datasheet PDFOctal D-type flip-flop Octal D-type flip-flop |
| Part Number | 74HCT374 |
|---|---|
| Description | Octal D-type flip-flop |
| Feature | 74HC374; 74HCT374
Octal D-type flip-flo p; positive edge-trigger; 3-state
Rev. 3 — 20 February 2018 Product data s heet 1 General description The 74HC374 ; 74HCT374 is an octal positive-edge tr iggered D-type flip-flop with 3‑state outputs. The device features a clock ( CP) and output enable (OE) inputs. The flip‑flops will store the state of th eir individual D-inputs that meet the s et-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A H IGH on OE causes the outputs to assume a high-impedance OFF-state. Operation o f the OE input does not affect the stat e of the flip-flops. . |
| Manufacture | nexperia |
| Datasheet |
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| Part Number | 74HCT374 |
|---|---|
| Description | Octal D-type flip-flop |
| Feature | INTEGRATED CIRCUITS
DATA SHEET
For a co mplete data sheet, please also download :
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74H C/HCT/HCU/HCMOS Logic Package Informati on • The IC06 74HC/HCT/HCU/HCMOS Logi c Package Outlines 74HC/HCT374 Octal D -type flip-flop; positive edge-trigger; 3-state Product specification File un der Integrated Circuits, IC06 December 1990 Philips Semiconductors Product s pecification Octal D-type flip-flop ; positive edge-trigger; 3-state FEATUR ES • 3-state non-inverting outputs fo r bus oriented applications • 8-bit p ositive, edge-triggered register . |
| Manufacture | Philips |
| Datasheet |
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| Part Number | 74HCT374 |
|---|---|
| Description | Octal D-Type Flip-Flop |
| Feature | CD54/74HC374, CD54/74HCT374, CD54/74HC57 4, CD54/74HCT574
Data sheet acquired f rom Harris Semiconductor SCHS183C
Febru ary 1998 - Revised May 2004
High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-S tate Positive-Edge Triggered
[ /Title (CD74 HC374 , CD74 HCT37 4, CD74 HC574 , CD74 HCT57
Features
Description
Buffered Inputs
• Common Three-Stat e Output Enable Control • Three-State Outputs • Bus Line Driving Capabilit y • Typical Propagation Delay (Clock to Q) = 15ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Ra nge) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Lo . |
| Manufacture | Texas Instruments |
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