74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 5 — 3 February 2016
Product data sheet
1. General description...
74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 5 — 3 February 2016
Product data sheet
1. General description
The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A Input levels:
For 74HC4040:
CMOS level For 74HCT4040: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Frequency...
