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74LS75 Datasheet

Part Number 74LS75
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Quad Latch
Datasheet 74LS75 Datasheet74LS75 Datasheet (PDF)

DM74LS75 Quad Latch August 1986 Revised March 2000 DM74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the.

  74LS75   74LS75






Part Number 74LS75
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description Quadruple Bistable Latches
Datasheet 74LS75 Datasheet74LS75 Datasheet (PDF)

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 *0.22 ± 0.05 0.20 ± 0.04 8 0.80 Max 2.20 Max 0.20 7.80 + – 0.30 1.15 0° – 8° 0.70 ± 0.20 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g *Dimension includin.

  74LS75   74LS75







Part Number 74LS75
Manufacturers Motorola
Logo Motorola
Description 4-BIT D LATCH
Datasheet 74LS75 Datasheet74LS75 Datasheet (PDF)

4-BIT D LATCH The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output un.

  74LS75   74LS75







Quad Latch

DM74LS75 Quad Latch August 1986 Revised March 2000 DM74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go HIGH. These latches feature complementary Q and Q outputs from a 4-bit latch, and are available in 16-pin packages. Ordering Code: Order Number DM74LS75M DM74LS75N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram (Each Latch) Connection Diagram Function Table Inputs D L H X (Each Latch) Outputs Q L H Q0 Q H L Q0 Enable H H L H = HIGH Level L = LOW Level X = Don't Care Q0 = The Level of Q Before the HIGH-to-LOW Transition of ENABLE © 2000 Fairchild Semiconductor Corporation DS006374 www.fairchildsemi.com DM74LS75 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Tempe.


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