74LV00

INTEGRATED CIRCUITS 74LV00 Quad 2-input NAND gate Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input NAND gate 74LV00 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Output capability: standard ICC category: SSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT00. The 74LV00 provides the 2-input NAND function. CONDITIONS CL = 15 pF; VCC = 3.3 V See Notes 1 and 2 TYPICAL 7 3.5 22 UNIT ns pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 fi )ȍ (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. ȍ (CL 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +1...