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74LVC1G125 Datasheet

Part Number 74LVC1G125
Manufacturers Diodes
Logo Diodes
Description SINGLE BUFFER GATE
Datasheet 74LVC1G125 Datasheet74LVC1G125 Datasheet (PDF)

74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description The 74LVC1G125 is a single, non-inverting buffer/bus driver with a 3-state output. The output enters a high-impedance state when a HIGH-level is applied to the output enable (OE) pin. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V, allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOF.

  74LVC1G125   74LVC1G125






Part Number 74LVC1G125
Manufacturers nexperia
Logo nexperia
Description Bus buffer/line driver
Datasheet 74LVC1G125 Datasheet74LVC1G125 Datasheet (PDF)

74LVC1G125 Bus buffer/line driver; 3-state Rev. 15 — 19 January 2022 Product data sheet 1. General description The 74LVC1G125 is a single buffer/line driver with 3-state output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications .

  74LVC1G125   74LVC1G125







Part Number 74LVC1G125
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description Bus buffer/line driver
Datasheet 74LVC1G125 Datasheet74LVC1G125 Datasheet (PDF)

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  74LVC1G125   74LVC1G125







SINGLE BUFFER GATE

74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description The 74LVC1G125 is a single, non-inverting buffer/bus driver with a 3-state output. The output enters a high-impedance state when a HIGH-level is applied to the output enable (OE) pin. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V, allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. Features  Wide Supply Voltage Range from 1.65 to 5.5V  ± 24mA Output Drive at 3.3V  CMOS Low Power Consumption  IOFF Supports Partial-Power-Down Mode Operation  Inputs Accept Up to 5.5V  ESD Protection Tested per JESD 22  Exceeds 200-V Machine Model (A115)  Exceeds 2000-V Human Body Model (A114)  Exceeds 1000-V Charged Device Model (C101)  Latch-Up Exceeds 100mA per JESD 78, Class I  Range of Package Options  Direct Interface with TTL Levels  Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)  Halogen and Antimony Free. “Green” Device (Note 3) Pin Assignments ( Top View ) ( Top View ) OE 1 A2 5 Vcc OE 1 A2 GND 3 5 Vcc 4Y GND 3 4Y SOT25 / SOT353 ( Top View ) OE 1 8 Vcc A 2 5 NC GND 3 4 Y X2-DFN1410-6 ( Bottom View ) GND 3 4Y A2 5 NC OE 1 6 Vcc X2-DFN1409-6 Chip Scale Alternative SOT553 (Top View ) OE 1 A2 6 Vcc 5 NC GND 3 4 Y X1-DFN1.


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