74LVC1G38-Q100
2-input NAND gate; open drain
Rev. 4 — 12 January 2022
Product data sheet
1. General description
The 74...
74LVC1G38-Q100
2-input NAND gate; open drain
Rev. 4 — 12 January 2022
Product data sheet
1. General description
The 74LVC1G38-Q100 is a single 2-input NAND gate with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and -40 °C to +125 °C
Wide supply
voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption Open drain outputs Direct interface with TTL levels Inputs accept
voltages up to 5 V Latch-up performance exceeds 250 mA Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V ...