74LVC2G125

74LVC2G125 Dual bus buffer/line driver; 3-state Rev. 14 — 29 March 2013 Product data sheet 1. General description The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant input/output for interfacing with 5 V logic  High noise immunity  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  24 mA output drive (VCC = 3.0 V)  CMOS low-power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C NXP Semiconductors 74LVC2G125 Dual bus buffer/line driver; 3-stat...