74LVCH162374A

INTEGRATED CIRCUITS DATA SHEET 74LVC162374A; 74LVCH162374A 16-bit edge triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state Product specification File under Integrated Circuits, IC24 1999 Aug 05 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 30 Ω series 74LVC162374A; termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374A FEATURES ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V 5 V tolerant input/output for interfacing with 5 V logic Wide supply voltage range of 1.2 to 3.6 V Complies with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTE™ flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH162374A only) High impedance when VCC = 0 Power off disables outputs, permitting live insertion. FUNCTION TABLE See note 1. INPUTS OPERATION MODES nOE Load and read register Latch register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH CP transition. L L H H nCP ↑ ↑ ↑ ↑ nDn l h l h INTERNAL FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 L H Z Z DESCRIPTION ...