74VCX1632245

www.DataSheet4U.com 74VCX1632245 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR I I I I I I I I I I I HIGH SPEED: tPD = 4.4ns (MAX.) at TA=85°C VCCA = 3.0V VCCB = 2.3V LOW POWER DISSIPATION: ICCA = ICCB = 20µA(MAX.) at TA=85°C SYMMETRICAL OUTPUT IMPEDANCE: |IOHA| = IOLA = 8mA MIN at VCCA = 3.0V VCCB = 1.65V or 2.3V |IOHA| = IOLA = 18mA MIN at VCCA = 2.3V VCCB = 1.65V) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL POWER DOWN PROTECTION ON INPUTS AND OUTPUTS 26Ω SERIES RESISTOR ON A SIDE OUTPUTS OPERATING VOLTAGE RANGE: VCCA(OPR) = 2.3V to 3.6V (1.2V Data Retention) VCCB(OPR) = 1.65V to 2.7V (1.2V Data Retention) MAX DATA RATES: 380 Mbps (1.8V to 3.3V translation) 260 Mbps (<1.8V to 3.3V translation) 260 Mbps (Translate to 2.5V) 210 Mbps (Translate to 1.5V) 100 Mbps (Translate to 1.2V) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16245 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V TSSOP TFBGA µTFBGA Table 1: Order Codes PACKAGE TSSOP48 TFBGA54 µTFBGA42 T&R 74VCX1632245TTR 74VCX1632245LBR 74VCX1632245TBR isolated. The A-port interfaces with the 3V bus, the B-port with the 2.5V and 1.8V bus. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. All floating bus terminals during High Z State must be held HIGH or LOW. Figure 1: Logic Diagram DESCRIPTION The 74VCX1632245 is a dual supply low voltage CMO...