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74VHCT126 Datasheet

Part Number 74VHCT126
Manufacturers nexperia
Logo nexperia
Description Quad buffer/line driver
Datasheet 74VHCT126 Datasheet74VHCT126 Datasheet (PDF)

74VHC126; 74VHCT126 Quad buffer/line driver; 3-state Rev. 2 — 6 April 2020 Product data sheet 1. General description The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes th.

  74VHCT126   74VHCT126






Part Number 74VHCT126
Manufacturers NXP
Logo NXP
Description Quad buffer/line driver
Datasheet 74VHCT126 Datasheet74VHCT126 Datasheet (PDF)

74VHC126; 74VHCT126 Quad buffer/line driver; 3-state Rev. 01 — 13 August 2009 Product data sheet 1. General description The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes.

  74VHCT126   74VHCT126







Quad buffer/line driver

74VHC126; 74VHCT126 Quad buffer/line driver; 3-state Rev. 2 — 6 April 2020 Product data sheet 1. General description The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC126; 74VHCT126 are identical to the 74VHC125; 74VHCT125 but have active HIGH output enable inputs. 2. Features • Balanced propagation delays • All inputs have Schmitt-trigger action • Inputs accept voltages higher than VCC • Input levels: • The 74VHC126 operates with CMOS input level • The 74VHCT126 operates with TTL input level • ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74VHC126D 74VHCT126D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74VHC126PW 74VHCT126PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74VHC126BQ 74VHCT126BQ -40 °C to +125 °C DHVQFN14 plasti.


2019-07-25 : 74LVC1G16    74LVC1G34    74LVC1G126    74LVC1GU04    74ABT16245B    74ALVC164245    74AUP1T34    74AUP1T17    PH9496NL    74ABT16244A   


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