79RC32351

IDTTM InterpriseTM Integrated Communications Processor 79RC32351 Features List RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8kB Instruction cache, 2-way set associative www.DataSheet4U.com – 2kB Data cache, 2-way set associative – Per line cache locking – Write-through and write-back cache management – Debug interface through the EJTAG port – Big or little endian support ◆ Interrupt Controller – Allows status of each interrupt to be read and masked ◆ UARTs – Two 16550 Compatible UARTs – Baud rate support up to 1.5 Mb/s ◆ Counter/Timers – Three general purpose 32-bit counter/timers ◆ General Purpose I/O Pins (GPIOP) – 32 individually programmable pins: each pin programmable as input, output, or alternate function, input can be an interrupt or NMI source, input can also be active high or active low – 4 additional, auxiliary GPIO pins can be configured as input or output ◆ SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers – Automatic refresh generation ◆ Peripheral Device Controller – 26-bit address bus – 32-bit data bus with variable width support of 8-,16-, or 32-bits – 8-bit boot ROM support – 6 banks available, up to 64MB per bank – Supports Flash ROM, PROM, SRAM, dual-port memory, and peripheral devices – Supports external wait-state...