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8051 Datasheet

8 BIT CONTROL ORIENTED MICROCOMPUTERS

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INTEL
8051.pdf

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INTEL 8051 Datasheet

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C8051F330/1/2/3/4/5 Mixed Signal ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (‘F330/2/4 only) • Up to 200 ksps • Up to 16 external single-ended or differential inputs • VREF from internal VREF, external pin or VDD • Internal or external start of conversion source • Built-in temperature sensor - 10-Bit Current Output DAC (‘F330 only) - Comp.


Silicon Laboratories
8051F330.pdf

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Silicon Laboratories 8051F330 Datasheet

C8051F330/1/2/3/4/5 Mixed Signal ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (‘F330/2/4 only) • Up to 200 ksps • Up to 16 external single-ended or differential inputs • VREF from internal VREF, external pin or VDD • Internal or external start of conversion source • Built-in temperature sensor - 10-Bit Current Output DAC (‘F330 only) - Comparator • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current (0.4 µA) On-Chip Debug www.DataSheet4U.com - On-chip debug circuitry facilitates full speed, nonintrusive in-system debug (no emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Low cost, complete development kit High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 76.






C8051F310/1/2/3/4/5/6/7 8/16 kB ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (C8051F310/1/2/3/6 only) • • • • • High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 200 ksps Up to 21, 17, or 13 external single-ended or differential inputs VREF from external pin or VDD Bui.


Silicon Laboratories
8051F310.pdf

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Silicon Laboratories 8051F310 Datasheet

C8051F310/1/2/3/4/5/6/7 8/16 kB ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (C8051F310/1/2/3/6 only) • • • • • High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 200 ksps Up to 21, 17, or 13 external single-ended or differential inputs VREF from external pin or VDD Built-in temperature sensor External conversion start input Programmable hysteresis and response time Configurable as interrupt or reset source (Comparator0) Low current ( 0.5 µA) - Comparators • • • - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 1280 bytes internal data RAM (1024 + 256) - 16 kB (C8051F310/1/6/7) or 8 kB (C8051F312/3/4/5) Flash; In-system programmable in 512-byte sectors On-Chip Debug - On-chip debug circuitry facilitates full speed, - Digital Peripherals - 29/25/21 Port I/O;  All 5 V tolerant with high sink current Hardware enhanced UART, SMBus™, and SPI™ serial ports Four general purp.








 

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