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8051F023 Datasheet

Part Number 8051F023
Manufacturers ETC
Logo ETC
Description C8051F023
Datasheet 8051F023 Datasheet8051F023 Datasheet (PDF)

  8051F023   8051F023
C8051F020/1/2/3 8K ISP FLASH MCU Family ANALOG PERIPHERALS - SAR ADC • 12-Bit (C8051F020/1) • 10-Bit (C8051F022/3) • ± 1 LSB INL • Programmable Throughput up to 100 ksps • Up to 8 External Inputs; Programmable as Single-Ended or Differential • Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5 • Data-Dependent Windowed Interrupt Generator • Built-in Temperature Sensor (± 3°C) - 8-bit ADC • Programmable Throughput up to 500 ksps • 8 External Inputs • Programmable Amplifier Gain: 4, 2, 1, 0.5 - Two 12-bit DACs • Can Synchronize Outputs to Timers for Jitter-Free Wave- form Generation - Two Analog Comparators - Voltage Reference - Precision VDD Monitor/Brown-Out Detector ON-CHIP JTAG DEBUG & BOUNDARY SCAN - On-Chip Debug Circuitry Facilitates Full- Speed, Non- Intrusive In-Circuit/In-System Debugging - Provides Breakpoints, Single-Stepping, Watchpoints, Stack Monitor; Inspect/Modify Memory and Registers - Superior Performance to Emulation Systems Using ICE- Chips, Target Pods, and Sockets -.






C8051F023

C8051F020/1/2/3 8K ISP FLASH MCU Family ANALOG PERIPHERALS - SAR ADC • 12-Bit (C8051F020/1) • 10-Bit (C8051F022/3) • ± 1 LSB INL • Programmable Throughput up to 100 ksps • Up to 8 External Inputs; Programmable as Single-Ended or Differential • Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5 • Data-Dependent Windowed Interrupt Generator • Built-in Temperature Sensor (± 3°C) - 8-bit ADC • Programmable Throughput up to 500 ksps • 8 External Inputs • Programmable Amplifier Gain: 4, 2, 1, 0.5 - Two 12-bit DACs • Can Synchronize Outputs to Timers for Jitter-Free Wave- form Generation - Two Analog Comparators - Voltage Reference - Precision VDD Monitor/Brown-Out Detector ON-CHIP JTAG DEBUG & BOUNDARY SCAN - On-Chip Debug Circuitry Facilitates Full- Speed, Non- Intrusive In-Circuit/In-System Debugging - Provides Breakpoints, Single-Stepping, Watchpoints, Stack Monitor; Inspect/Modify Memory and Registers - Superior Performance to Emulation Systems Using ICE- Chips, Target Pods, and Sockets - IEEE1149.1 Compliant Boundary Scan - Low-Cost, Complete Development Kit HIGH SPEED 8051 µC CORE - Pipelined Instruction Architecture; Executes 70% of Instruction Set in 1 or 2 System Clocks - Up to 25 MIPS Throughput with 25 MHz Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (4k + 256) - 64k Bytes FLASH; In-System programmable in 512-byte Sectors - External 64k Byte Data Memory Interface (programma- ble multiplexed or non-multiplexed modes) DIGITAL PERIPHERALS - 8 .



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