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9DB1904B Datasheet

Part Number 9DB1904B
Manufacturers Renesas
Logo Renesas
Description 19 Output Differential Buffer
Datasheet 9DB1904B Datasheet9DB1904B Datasheet (PDF)

Datasheet 19 Output Differential Buffer for PCIe Gen2 and QPI 9DB1904B Description The 9DB1904 is electrically compatible to the Intel DB1900GS Differential Buffer Specification. This buffer provides 19 output clocks for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential clock from a CK410B+ main clock generator, such as the ICS932S421 drives the 9DB1904. The 9DB1904 can provide outputs up to 400MHz in Bypass Mode. Recommended Application 19 Output Differential Buffer for PCIe.

  9DB1904B   9DB1904B






Part Number 9DB1904B
Manufacturers IDT
Logo IDT
Description 19 Output Differential Buffer
Datasheet 9DB1904B Datasheet9DB1904B Datasheet (PDF)

Datasheet 19 Output Differential Buffer for PCIe Gen2 and QPI 9DB1904B Description The 9DB1904 is electrically compatible to the Intel DB1900GS Differential Buffer Specification.This buffer provides 19 output clocks for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential clock from a CK410B+ main clock generator, such as the ICS932S421 drives the 9DB1904. The 9DB1904 can provide outputs up to 400MHz in Bypass Mode. Recommended Application 19 Output Differential Buffer for PCIe .

  9DB1904B   9DB1904B







19 Output Differential Buffer

Datasheet 19 Output Differential Buffer for PCIe Gen2 and QPI 9DB1904B Description The 9DB1904 is electrically compatible to the Intel DB1900GS Differential Buffer Specification. This buffer provides 19 output clocks for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential clock from a CK410B+ main clock generator, such as the ICS932S421 drives the 9DB1904. The 9DB1904 can provide outputs up to 400MHz in Bypass Mode. Recommended Application 19 Output Differential Buffer for PCIe Gen2 and QPI Key Specifications • DIF output cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 150ps across all outputs Features/Benefits • Power up default is all outputs in 1:1 mode/No SMBus programming • Spread spectrum compatible/EMI reductions • Supports output frequencies up to 400 MHz in bypass mode/flexible fanout buffer • 8 Selectable SMBus addresses/no SMBus segmentation required • SMBus address determines PLL or Bypass mode/pin savings • Dedicated VDDA and CKPWRGD_PD# pins/easy board design Functionality at Power Up (PLL Mode) 100M_133M# CLK_IN MHz 1 100MHz 0 133MHz Pin Configuration DIF_(18:0) MHz CLK_IN CLK_IN Power Down Functionality INPUTS CKPWRGD_ CLK_IN/ PD# CLK_IN# 1 Running 0 X OUTPUTS DIF/DIF# Running Hi-Z PLL State ON OFF SMB_A2_PLLBYP# CLK_IN# CLK_IN OE17_18# DIF_18# DIF_18 DIF_17# DIF_17 GND VDD DIF_16# DIF_ 16 OE15_16# DIF_15# DIF_15 CKPWRGD_PD# DIF_14# DIF_14 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF 1 GNDA 2 .


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