9DBL0252

2-output 3.3V PCIe Zero-Delay Buffer 9DBL0242 / 9DBL0252 DATASHEET Description The 9DBL0242 / 9DBL0252 devices are 3.3V members of IDT's Full-Featured PCIe family. The devices support PCIe Gen1-4 Common Clocked (CC) and PCIe Gen2 Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85 or 100 transmission lines. The 9DBL02P2 can be factory programmed with a user-defined power up default SMBus configuration. Recommended Application PCIe Gen1-4 clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features 2 – 1-200 MHz Low-Power (LP) HCSL DIF pairs 9DBL0242 default ZOUT = 100 9DBL0252 default ZOUT = 85 9DBL02P2 factory programmable defaults Easy AC-coupling to other logic families, see IDT application note AN-891 Key Specifications PCIe Gen1-2-3-4 CC compliant in ZDB mode PCIe Gen2 SRIS compliant in ZDB mode Su...