9DBL0641

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Description The 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 buffers are low-power, high-performance members of Renesas' full featured PCIe family. The buffers support PCIe Gen1 through Gen5. PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) Typical Applications ▪ PCIe Riser Cards ▪ nVME Storage ▪ Networking ▪ Accelerators ▪ Industrial Control/Embedded Features ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE# pin for each output ▪ 1MHz to 200MHz operation in fan-out mode ▪ 3 selectable SMBus addresses ▪ Extensive SMBus-selectable features allow optimization to customer requirements ▪ SMBus interface not required for device operation ▪ -40°C to +85°C operating temperature range ▪ Space-saving 4 × 4 mm 24-VFQFPN to 6 × 6 mm 48-VFQFPN packages (see Ordering Information table for details) Key Specifications ▪ Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode) ▪ PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode) Block Diagram PLL CLK_IN# CLK_IN vSADR_tri SCLK_3.3 SDATA_3.3 ^vHIBW_BYPM-LOBW# ^CKPW RGD_PD # vOE[n:0]# SMBus Factory Engine Configuration Control Logic n+1 FB...