9DBU0641 Datasheet | IDT





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9DBU0641 Datasheet PDF

Part Number 9DBU0641
Description 6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 17 Pages
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Features: Datasheet pdf 6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB w/Zo=10 0ohms 9DBU0641 DATASHEET Description The 9DBU0641 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It h as integrated output terminations provi ding Zo=100 for direct connection to 100 transmission lines. The device has 6 output enables for clock manageme nt and 3 selectable SMBus addresses. Re commended Application 1.5V PCIe Gen1-2- 3 Zero Delay/Fanout Buffer (ZDB/FOB) Ou tput Features • 6 – 1-167MHz Low-Po wer (LP) HCSL DIF pairs w/Zo=100 Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output s kew <60ps • DIF phase jitter is PCIe Gen1-2-3 compliant • DIF bypass mode additive phase jitter is <300fs rms for PCIe Gen3 • DIF bypass mode additive phase jitter <350fs rms for 12k-20MHz Block Diagram vOE(5:0)# 6 Features/B enefits • Direct connection to 100 transmission lines; saves 24 resistors compared to standard HCSL outputs • 46mW typical power consumption in PLL mode; eliminates thermal .

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9DBU0641 Datasheet
6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0641
DATASHEET
Description
The 9DBU0641 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100for direct connection to 100
transmission lines. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
6 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <60ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
vOE(5:0)#
6
Features/Benefits
Direct connection to 100transmission lines; saves 24
resistors compared to standard HCSL outputs
46mW typical power consumption in PLL mode; eliminates
thermal concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimze PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0641 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.

9DBU0641 Datasheet
9DBU0641 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
^vHIBW_BYPM_LOBW# 2
29 vOE3#
FB_DNC 3
28 DIF3#
FB_DNC# 4
VDDR1.5 5
9DBU0641
27 DIF3
26 VDDIO
CLK_IN 6
CLK_IN# 7
epad is GND
25 VDDA1.5
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
40-VFQFPN, 5mm x 5mm 0.4mm pin pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
True O/P Comp. O/P
0 X X X Low Low
1
Running
0
X Low Low
1
Running
1
0 Running Running
1
Running
1
1 Low Low
1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table.
PLL
Off
On1
On1
On1
Power Connections
Pin Number
VDD
VDDIO
5
11
16, 31
25
12,17,26,32,
39
GND
41
8
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
6 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
2
REVISION C 04/22/15




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