9DBV0241

2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer with Zo=100ohms 9DBV0241 DATASHEET Description The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Recommended Application 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features 2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs w/ZO=100 Key Specifications DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF additive phase jitter is <100fs rms for PCIe Gen3 DIF additive phase jitter <300fs rms (12k-20MHz) Block Diagram Features/Benefits LP-HCSL outputs with Zo=100; saves 8 resistors compared to standard HCSL output 35mW typical power consumption in PLL mode; minimal power consumption Spread Spectrum (SS) compatible; allows use of SS for EMI reduction OE# pins; support DIF power management HCSL compatible differential input; can be driven by common clock sources SMBus-sele...