Buffer. 9DBV0931 Datasheet

9DBV0931 Datasheet PDF


Part

9DBV0931

Description

9-output 1.8V HCSL Fanout Buffer

Manufacture

IDT

Page 18 Pages
Datasheet
Download 9DBV0931 Datasheet


9DBV0931 Datasheet
9-Output 1.8V HCSL Fanout Buffer
9DBV0931
DATASHEET
Description
The 9DBV0931 is a member of IDT's Full-Featured PCIe
family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
PCIe Gen1–3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
9 1–200MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 60ps
Additive phase jitter is < 100fs rms for PCIe Gen3
Additive phase jitter < 300fs rms (12kHz-20MHz
at125MHz)
Block Diagram
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
LP-HCSL outputs; save 18 resistors and 31mm2 compared
to standard HCSL
53mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
6 x 6 mm 48-VFQFPN; minimal board space
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0931 MARCH 14, 2017
1 ©2017 Integrated Device Technology, Inc.

9DBV0931 Datasheet
9DBV0931 DATASHEET
Pin Configuration
vSADR_tri 1
vOE8# 2
DIF8 3
DIF8# 4
VDDR1.8 5
CLK_IN 6
CLK_IN# 7
GNDR 8
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
VDDDIG1.8 12
48 47 46 45 44 43 42 41 40 39 38 37
9DBV0931
connect epad to
ground
13 14 15 16 17 18 19 20 21 22 23 24
36 DIF5#
35 DIF5
34 vOE4#
33 DIF4#
32 DIF4
31 VDDIO
30 VDD1.8
29 GND
28 vOE3#
27 DIF3#
26 DIF3
25 vOE2#
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VD
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SADR
0
M
1
Address
1101011
1101100
1101101
CKPWRGD_PD#
CLK_IN
0X
1 Running
1 Running
1 Running
Power Connections
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
Pin Number
VDD
5
12
20,30,31,38
VDDIO
13,21,31,39,
47
GND
8
9
Description
Input
receiver
analog
Digital power
22,29,40 DIF outputs
+ Read/Write bit
x
x
x
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running
Running
Low Low
9-OUTPUT 1.8V HCSL FANOUT BUFFER
2
MARCH 14, 2017


Features Datasheet pdf 9-output 1.8V HCSL Fanout Buffer 9DBV09 31 DATASHEET Description The 9DBV0931 is a member of IDT's Full-Featured PCI e family. The device has 9 output enabl es for clock management, and 3 selectab le SMBus addresses. Recommended Applica tion PCIe Gen1-3 clock distribution in Storage, Networking, Compute, Consumer Output Features • 9 - 1-200MHz Low-Po wer (LP) HCSL DIF pairs Key Specificati ons • Additive cycle-to-cycle jitter <5ps • Output-to-output skew < 60ps Additive phase jitter is <100fs rms for PCIe Gen3 • Additive phase jitter <300fs rms (12kHz-20MHz @125MHz) Block Diagram Features/Benefits • LP-HCSL outputs; save 18 resistors and 31mm2 c ompared to standard HCSL • 53mW typic al power consumption; eliminates therma l concerns • Outputs can optionally b e supplied from any voltage between 1.0 5V and 1.8V; maximum power savings • OE# pins; support DIF power management • HCSL-compatible differential input; can be driven by common clock sources • SMBus-selectable fea.
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