Part Number

9DMU0441

Description

2:4 1.5V PCIe Gen1-2-3 Clock Mux

Manufacture

IDT

Total Page 11 Pages
PDF Download
Download 9DMU0441 Datasheet


Features Datasheet pdf 2:4 1.5V PCIe Gen1-2-3 Clock Mux w/Zo=10 0ohms 9DMU0441 DATASHEET General Desc ription The 9DMU0441 is a member of IDT 's SOC-Friendly 1.5V Ultra-Low-Power (U LP) PCIe Gen1-2-3 family. It has integr ated output terminations providing Zo=1 00ohms for direct connection to 100ohm transmission lines. Each of the 4 outpu ts has its own dedicated OE# pin for op timal system control and power manageme nt. The part provides asynchronous and glitch-free switching modes. Recommende d Application 2:4 PCIe Gen1-2-3 clock m ultiplexer Output Features • 4 – Lo w-Power (LP) HCSL DIF pairs w/Zo=100 Key Specifications • DIF additive cy cle-to-cycle jitter <5ps • DIF phase jitter is PCIe Gen1-2-3 compliant • A dditive phase jitter @ 125MHz: 535fs rm s typical (12kHz to 20MHz) • DIF outp ut-to-output skew <50ps Features/Benef its • LP-HCSL outputs w/integrated te rminations; saves 16 resistors compared to standard HCSL outputs • 1.5V oper ation; 26mW typical power consumption • Selectable asynchrono.
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9DMU0441 Datasheet
2:4 1.5V PCIe Gen1-2-3 Clock Mux
w/Zo=100ohms
9DMU0441
DATASHEET
General Description
The 9DMU0441 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100ohms for
direct connection to 100ohm transmission lines. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
4 – Low-Power (LP) HCSL DIF pairs w/Zo=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 535fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs w/integrated terminations; saves 16
resistors compared to standard HCSL outputs
1.5V operation; 26mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMU0441 REVISION A 09/24/14
1
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