9FGL0241

3.3V PCIe Gen1–5 Clock Generator Family 9FGL02x1/04x1/06x1/08x1 Datasheet Description The 9FGL02x1/04x1/06x1/08x1 devices comprise a family of 3.3V PCIe Gen1–5 clock generators. There are 2, 4, 6 and 8 outputs versions available and each differential output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) Typical Applications ▪ Servers/High-Performance Computing ▪ nVME Storage ▪ Networking ▪ Accelerators ▪ Industrial Control Output Features ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ 90fs RMS typical jitter (PCIe Gen5 CC) ▪ < 50ps cycle-to-cycle jitter on differential outputs ▪ < 50ps output-to-output skew on differential outputs ▪ ±0ppm synthesis error on differential outputs Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35% power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-selectable features allows optimization to customer requirements: Input polarity and pull-up/pull-downs Output slew rate and amplitude Output impedance (33Ω, 85Ω or 100Ω) for each output ▪ Contact factory for customized default configurations ▪...