Z-BUFFER. 9ZX21201 Datasheet

9ZX21201 Datasheet PDF


Part

9ZX21201

Description

12-OUTPUT DIFFERENTIAL Z-BUFFER

Manufacture

IDT

Page 16 Pages
Datasheet
Download 9ZX21201 Datasheet


9ZX21201 Datasheet
DATASHEET
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI 9ZX21201
General Description
The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express
Gen3 or QPI applications. The part is backwards compatible to
PCIe Gen1 and Gen2. A fixed external feedback maintains low drift
for critical QPI applications. In bypass mode, the IDT9ZX21201 can
provide outputs up to 150MHz.
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and newer
platforms
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 65 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Features/Benefits
• Space-saving 64-pin packages
• Fixed feedback path/ 0ps input-to-output delay
• 9 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• 100MHz or 133MHz PLL mode operation/supports PCIe
and QPI applications
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• Software control of PLL Bandwidth and Bypass Settings/
PLL can dejitter incoming clock (B Rev only)
Output Features
• 12 - 0.7V differential HCSL output pairs
Functional Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT
DIF(11:0)
Note: Even though the feedback is fixed, DFB_OUT still needs a
termination network for the part to function.
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
1
IREF
1682D - 11/19/15

9ZX21201 Datasheet
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 1
48 GND
GNDA 2
47 DIF_7#
IREF 3
46 DIF_7
100M_133M# 4
45 vOE7#
HIBW_BYPM_LOBW# 5
44 vOE6#
CKPWRGD_PD# 6
43 DIF_6#
GND 7
42 DIF_6
VDDR 8
DIF_IN 9
9ZX21201
41 GND
40 VDD
DIF_IN# 10
39 DIF_5#
SMB_A0_tri 11
38 DIF_5
SMBDAT 12
37 vOE5#
SMBCLK 13
36 vOE4#
SMB_A1_tri 14
35 DIF_4#
DFB_OUT# 15
34 DIF_4
DFB_OUT 16
33 GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Notes: Pins with ^ prefix have internal ~100K pullup
Pins with v prefix have internal ~100K pulldown.
Tri-level Input Thresholds
Level
Voltage
Low <0.8V
Mid 1.2<Vin<1.8V
High
Vin > 2.2V
Functionality at Power Up (PLL Mode)
100M_133M#
DIF_IN
(MHz)
1 100.00
0 133.33
DIF
DIF_IN
DIF_IN
PLL Operating Mode Readback Table
HiBW_BypM_LoBW# Byte0, bit 7
Low (Low BW)
0
Mid (Bypass)
0
High (High BW)
1
Byte 0, bit 6
0
1
1
PLL Operating Mode
HiBW_BypM_LoBW#
Low
Mid
MODE
PLL Lo BW
Bypass
High
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
MLF Power Connections
Pin Number
VDD
1
8
24,40,57
VDD
25,32,49,56
GND
2
7
23,33,41,48,
58
Description
Analog PLL
Analog Input
DIF clocks
9ZX21201 SMBus Addressing
Pin SMBus Address
SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0)
00
D8
0M
DA
0 1 DE
M0
C2
MM
C4
M1
C6
10
CA
1M
CC
11
CE
1682D- 11/19/15
2


Features Datasheet pdf DATASHEET 12-OUTPUT DIFFERENTIAL Z-BUFF ER FOR PCIE GEN2/3 AND QPI 9ZX21201 Ge neral Description The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Expr ess Gen3 or QPI applications. The part is backwards compatible to PCIe Gen1 an d Gen2. A fixed external feedback maint ains low drift for critical QPI applica tions. In bypass mode, the IDT9ZX21201 can provide outputs up to 150MHz. Recom mended Application 12-output PCIe Gen3/ QPI differential buffer for Romley and newer platforms Key Specifications • Cycle-to-cycle jitter <50ps • Output -to-output skew < 65 ps • Input-to-ou tput delay variation <50ps • PCIe Gen 3 phase jitter < 1.0ps RMS • QPI 9.6G T/s 12UI phase jitter < 0.2ps RMS Feat ures/Benefits • Space-saving 64-pin p ackages • Fixed feedback path/ 0ps in put-to-output delay • 9 Selectable SM Bus Addresses/Mulitple devices can shar e the same SMBus Segment • 12 OE# pin s/Hardware control of each output • P LL or bypass mode/PLL can dejitter incoming clock • 100MHz or.
Keywords 9ZX21201, datasheet, pdf, IDT, 12-OUTPUT, DIFFERENTIAL, Z-BUFFER, ZX21201, X21201, 21201, 9ZX2120, 9ZX212, 9ZX21, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent




@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)