buffer. 9ZXL0831 Datasheet

9ZXL0831 Datasheet PDF


Part

9ZXL0831

Description

Low-power 8-output differential buffer

Manufacture

IDT

Page 18 Pages
Datasheet
Download 9ZXL0831 Datasheet


9ZXL0831 Datasheet
8-OUTPUT DB800ZL
DATASHEET
9ZXL0831
General Description
The 9ZXL0831 is a low-power 8-output differential buffer
that meets all the performance requirements of the Intel
DB800ZL specification. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, SSD drives
and PCIe
Output Features
8 - LP-HCSL Output Pairs
Block Diagram
Features/Benefits
Low-power push-pull outputs; Save power and board
space - no Rp
Space-saving 48-pin VFQFPN package
Fixed feedback path for 0ps input-to-output delay
8 OE# pins; hardware control of each output
PLL or bypass mode; PLL can dejitter incoming clock
100MHz or 133MHz PLL mode operation; supports PCIe
and QPI applications
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
QPI/UPI 9.6GT/s 12UI phase jitter <0.2ps RMS
OE(7:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
Logic
SMBDAT
SMBCLK
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(7:0)
IDT® 8-OUTPUT DB800ZL
1
9ZXL0831
REV E 081616

9ZXL0831 Datasheet
9ZXL0831
8-OUTPUT DB800ZL
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
CKPWRGD_PD# 1
36 DIF_6#
GND 2
35 DIF_6
VDDR 3
34 VDD
DIF_IN 4
33 DIF_5#
DIF_IN# 5
9ZXL0831
32 DIF_5
SMBDAT 6
SMBCLK 7
Paddle is
pin 49
31 vOE5#
30 vOE4#
DFB_OUT_NC# 8
Connect to GND
29 DIF_4#
DFB_OUT_NC 9
28 DIF_4
VDD 10
27 VDD
vOE0# 11
26 DIF_3#
NC 12
25 DIF_3
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
Power Management Table
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
SMBus
EN bit
X
0
1
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
MHz
100.00
133.33
DIF(7:0)
DIF_IN
DIF_IN
Power Connections
Pin Number
VDD
44
3
10,15,19,
27,34,38, 42
GND
49
2
49
Description
Analog PLL
Analog Input
DIF clocks
SMBus Address
Address
1101100
+ Read/Write bit
x
DIF(7:0)/
DIF(7:0)#
Low/Low
Low/Low
Running
PLL STATE
IF NOT IN
BYPASS
MODE
OFF
ON
ON
PLL Operating Mode Readback Table
HiBW_BypM_LoBW#
Low (Low BW)
Mid (Bypass)
High (High BW)
Byte0, bit 7
0
0
1
Byte 0, bit 6
0
1
1
Tri-Level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
PLL Operating Mode
HiBW_BypM_LoBW#
MODE
Low PLL Lo BW
Mid
High
Bypass
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
IDT® 8-OUTPUT DB800ZL
2
9ZXL0831
REV E 081616


Features Datasheet pdf 8-OUTPUT DB800ZL DATASHEET 9ZXL0831 Ge neral Description The 9ZXL0831 is a low -power 8-output differential buffer tha t meets all the performance requirement s of the Intel DB800ZL specification. I t is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fix ed external feedback to maintain low dr ift for demanding QPI/UPI applications. Recommended Application Buffer for Rom ley, Grantley and Purley Servers, SSD d rives and PCIe Output Features • 8 - LP-HCSL Output Pairs Block Diagram Fea tures/Benefits • Low-power push-pull outputs; Save power and board space - n o Rp • Space-saving 48-pin VFQFPN pac kage • Fixed feedback path for 0ps in put-to-output delay • 8 OE# pins; har dware control of each output • PLL or bypass mode; PLL can dejitter incoming clock • 100MHz or 133MHz PLL mode op eration; supports PCIe and QPI applicat ions • Selectable PLL bandwidth; mini mizes jitter peaking in downstream PLL' s • Spread Spectrum Compatible; tracks spreading input clock .
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