9ZXL1232E Datasheet


Part Number

9ZXL1232E

Description

12-output DB1200ZL Derivative

Manufacture

IDT

Total Page 21 Pages
PDF Download
Download 9ZXL1232E Datasheet


Features Datasheet pdf 12-Output DB1200ZL Derivative for PCIe Gen1–4 and UPI with 9ZXL1232E / 9ZXL1 252E Write Lock Datasheet Descriptio n The 9ZXL1232E / 9ZXL1252E are second- generation, enhanced-performance DB1200 ZL differential buffers. The parts are pin-compatible upgrades to the 9ZXL1232 A and 9ZLX1252A, while offering a much improved phase jitter performance and a n SMBus Write Lock feature for increase d system security. A fixed external fee dback maintains low drift for critical QPI/UPI applications. The 9ZXL1232E and 9ZXL1252E have an SMBus Write Lockout pin for increased device and system sec urity. PCIe Clocking Architectures Supp orted ▪ Common Clocked (CC) ▪ Indep endent Reference (IR) with and without spread spectrum Typical Applications Servers ▪ Storage ▪ Networking SSDs Output Features ▪ 12 Low-Power (LP) HCSL output pairs (1232E) ▪ 12 Low-Power (LP) HCSL output pairs with 8 5Ω Zout (1252E) Block Diagram VDDR VDDA Features ▪ SMBus write lock feature; increases system .
Keywords 9ZXL1232E, datasheet, pdf, IDT, 12-output, DB1200ZL, Derivative, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

9ZXL1232E Datasheet
12-Output DB1200ZL Derivative
for PCIe Gen1–4 and UPI with 9ZXL1232E / 9ZXL1252E
Write Lock
Datasheet
Description
The 9ZXL1232E / 9ZXL1252E are second-generation,
enhanced-performance DB1200ZL differential buffers. The parts
are pin-compatible upgrades to the 9ZXL1232A and 9ZLX1252A,
while offering a much improved phase jitter performance and an
SMBus Write Lock feature for increased system security. A fixed
external feedback maintains low drift for critical QPI/UPI
applications. The 9ZXL1232E and 9ZXL1252E have an SMBus
Write Lockout pin for increased device and system security.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
Networking
SSDs
Output Features
12 Low-Power (LP) HCSL output pairs (1232E)
12 Low-Power (LP) HCSL output pairs with 85Zout (1252E)
Block Diagram
VDDR
VDDA
Features
SMBus write lock feature; increases system security
LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area
(1232E)
LP-HCSL outputs with 85Zout; eliminate 48 resistors, save
82mm2 of area (1252E)
12 OE# pins; hardware control of each output
9 selectable SMBus addresses; multiple devices can share the
same SMBus segment
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for
EMI reduction
100 and 133.33 MHz PLL mode; UPI and legacy QPI support
9 x 9 mm 64-QFN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: Fixed at 0ps
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: QPI/UPI > 9.6GB/s < 0.2ps rms
Phase jitter: IF-UPI < 1.0ps rms
VDD x3
VDDIO x4
DIF_IN#
DIF_IN
PLL
FBOUT_NC#
FBOUT_NC
DIF11#
DIF11
^100M_133M#
vSADR[1:0]_tri
SMBCLK
SMBDAT
vSMB_WRTLOCK
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[11:0]#
©2018 Integrated Device Technology, Inc
SMBus Factory
Engine Configuration
12
outputs
Control Logic
Resistors are integrated on 9ZXL125x devices and
external on 9ZXL123x devices
GNDA
GND x7
DIF0#
DIF0
1
November 30, 2018




@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)