A3S12D40ETP

512Mb DDR SDRAM Specification A3S12D30ETP A3S12D40ETP Powerchip Semiconductor Corp. No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu Taiwan, R.O.C. TEL:886-3-5795000 FAX:886-3-5792168 Free Datasheet http://www.datasheet4u.net/ Powerchip Semiconductor Corporation A3S12D30/40ETP 512Mb DDR Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, A3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The A3S12D30/40ETP achieves very high speed data rate up to 200MHz, and are suitable for main memory in computer systems. FEATURES - Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5) - Vdd=Vddq=2.6V+0.1V (for speed grade -5) - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - Four internal banks for concurrent opertation - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5/3.0 (programmable) - Burst length- 2/4/8 (pr...