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A43L2632 Datasheet

Part Number A43L2632
Manufacturers AMIC Technology
Logo AMIC Technology
Description 1M X 32 Bit X 4 Banks Synchronous DRAM
Datasheet A43L2632 DatasheetA43L2632 Datasheet (PDF)

www.DataSheet4U.com A43L2632 Preliminary Document Title 1M X 32 Bit X 4 Banks Synchronous DRAM Revision History Rev. No. 0.0 1M X 32 Bit X 4 Banks Synchronous DRAM History Initial issue Issue Date January 13, 2005 Remark Preliminary PRELIMINARY (January, 2005, Version 0.0) AMIC Technology, Corp. A43L2632 Preliminary Features JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Le.

  A43L2632   A43L2632






1M X 32 Bit X 4 Banks Synchronous DRAM

www.DataSheet4U.com A43L2632 Preliminary Document Title 1M X 32 Bit X 4 Banks Synchronous DRAM Revision History Rev. No. 0.0 1M X 32 Bit X 4 Banks Synchronous DRAM History Initial issue Issue Date January 13, 2005 Remark Preliminary PRELIMINARY (January, 2005, Version 0.0) AMIC Technology, Corp. A43L2632 Preliminary Features JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Deep Power Down Mode Burst Read Single-bit Write operation Clock Frequency (max) : 166MHz @ CL=3 (-6) 143MHz @ CL=3 (-7) 1M X 32 Bit X 4 Banks Synchronous DRAM DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Self refresh with programmable refresh period through EMRS cycle Programmable Power Reduction Feature by partial array activation during Self-refresh through EMRS cycle 86 Pin TSOP (II) operating temperature range: 0ºC to + 70ºC General Description The A43L2632 is 67,108,864 bits Low Power synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 32 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same d.


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