A625308

www.DataSheet4U.com A625308 Series Preliminary Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. 0.0 0.1 0.2 32K X 8 BIT CMOS SRAM History Initial issue Erase 28-pin DIP package type Erase 55ns part Issue Date June 30, 1998 May 21, 1999 December 1, 2000 Remark Preliminary PRELIMINARY (December, 2000, Version 0.2) AMIC Technology, Inc. A625308 Series Preliminary Features n External Operating Voltage: 4.5V to 5.5V n Access times: 70 ns (max.) n Current: A625308-L series: Operating: 70mA (max.) Standby: 100µA (max.) A625308-S series: Operating: 70mA (max.) Standby: 25µA (max.) n n n n n Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2.0V (min.) Available in 28-pin SOP and TSOP (forward and reverse type) packages 32K X 8 BIT CMOS SRAM General Description The A625308 is a low operating current 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2.0V. Pin Configurations n SOP n TSOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 28 27 26 25 24 VCC WE A13 A8 A9 A11 OE ...