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A62S7316 Datasheet

Part Number A62S7316
Manufacturers AMIC Technology
Logo AMIC Technology
Description 128K X 16 BIT LOW VOLTAGE CMOS SRAM
Datasheet A62S7316 DatasheetA62S7316 Datasheet (PDF)

A62S7316 Series Preliminary Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 0.2 128K X 16 BIT LOW VOLTAGE CMOS SRAM History Initial issue Modify VCCmax from 3.3V to 3.6V Add 55ns grade spec. for VCC = 3.0V to 3.6V Issue Date November 24, 1999 December 20, 2000 March 23, 2001 Remark Preliminary PRELIMINARY (March, 2001, Version 0.2) AMIC Technology, Inc. A62S7316 Series Preliminary Features n Operating voltage: 2.7V to 3.6V n Access times: 55ns (max.):.

  A62S7316   A62S7316






128K X 16 BIT LOW VOLTAGE CMOS SRAM

A62S7316 Series Preliminary Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 0.2 128K X 16 BIT LOW VOLTAGE CMOS SRAM History Initial issue Modify VCCmax from 3.3V to 3.6V Add 55ns grade spec. for VCC = 3.0V to 3.6V Issue Date November 24, 1999 December 20, 2000 March 23, 2001 Remark Preliminary PRELIMINARY (March, 2001, Version 0.2) AMIC Technology, Inc. A62S7316 Series Preliminary Features n Operating voltage: 2.7V to 3.6V n Access times: 55ns (max.): for VCC = 3.0V to 3.6V 70ns (max.): for VCC = 2.7V to 3.6V n Current: A62S7316-S series: Operating: 50mA (max.) Standby: 10µA (max.) A62S7316-SI series: Operating: 50mA (max.) Standby: 15µA (max.) n Extended operating temperature range : -25°C to 85°C for -SI series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 44-pin TSOP and 48-ball Mini BGA (6X8) packages. 128K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The A62S7316 is a low operating current 2,097,152-bit static random access memory organized as 131,072 words by 16 bits and operates on low power supply voltage from 2.7V to 3.6V. It is built using AMIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byt.


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