A67L83161

A67L83161/A67L83181/ A67L73321/A67L73361 Series 256K X 16/18, 128K X 32/36 Preliminary Document Title 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBATM SRAM Revision History Rev. No. 0.0 0.1 LVTTL, Flow-through DBATM SRAM History Initial issue Change fast access time from 7.5/8.0/8.5/9.0 ns to 10/11/12 ns Change set-up time from 2.0/2.2/2.5 ns to 2.5 ns Fix pin assignment error for pin 14 and pin 16 Issue Date April 7, 1999 September 15, 1999 Remark Preliminary PRELIMINARY (September, 1999, Version 0.1) AMIC Technology, Inc. DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc A67L83161/A67L83181/ A67L73321/A67L73361 Series 256K X 16/18, 128K X 32/36 Preliminary Features n Fast access time: 10/11/12 ns (100, 90, 83 MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.3V ± 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Internally self-timed write cycle n Selectable BURST mode (Linear or Interleaved) n SLEEP mode (ZZ pin) provided n Available in 100 pin LQFP package LVTTL, Flow-through DBATM SRAM General Description The AMIC Direct Bus Alternation™ (DBA™) SRAM family employs high-speed, low-power CMOS designs using an ...