A67L93361

A67L06181/A67L93361 Preliminary Document Title 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM History Initial issue Issue Date August, 20, 2005 Remark Preliminary PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. A67L06181/A67L93361 Preliminary Features Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) control...