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A67P9318 Datasheet

Part Number A67P9318
Manufacturers AMIC Technology
Logo AMIC Technology
Description (A67P8336 / A67P9318) Pipelined ZeBL SRAM
Datasheet A67P9318 DatasheetA67P9318 Datasheet (PDF)

www.DataSheet4U.com A67P9318/A67P8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A67P9318/A67P8336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% .

  A67P9318   A67P9318






Part Number A67P93181
Manufacturers AMIC Technology
Logo AMIC Technology
Description (A67P83361 / A67P93181) Flow-through ZeBL SRAM
Datasheet A67P9318 DatasheetA67P93181 Datasheet (PDF)

www.DataSheet4U.com A67P93181/A67P83361 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM History Initial issue Issue Date July 12, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A67P93181/A67P83361 Preliminary Features Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus util.

  A67P9318   A67P9318







(A67P8336 / A67P9318) Pipelined ZeBL SRAM

www.DataSheet4U.com A67P9318/A67P8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A67P9318/A67P8336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P9318, A67P8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered singl.


2006-12-01 : A43L1616    A43L1632    A43L2616    A43L2616A    A43L2632    A64E06161    A64E16161    A67P0618    A67P9336    A67P06361   


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