ACS541MS

ACS541MS January 1996 Radiation Hardened Octal Buffer/ Line Driver Three-State Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW OE1 A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 Features Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96710 and Intersil’s QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm /mg Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse Dose Rate Survivability . . . . . . . . . . . >10 Latch-Up Free Under Any Conditions Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min Input Current ≤ 1µA at VOL, VOH Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ) 12 2 RAD (Si)/s, 20ns Pulse GND 10 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW OE1 A0 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VC...