ACS630MS

ACS630MS January 1996 Radiation Hardened EDAC (Error Detection and Correction Circuit) Pinouts 28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835 DESIGNATOR CDIP2-T28, LEAD FINISH C TOP VIEW DEF 1 DB0 2 DB1 3 DB2 4 DB3 5 DB4 6 DB5 7 DB6 8 28 VCC 27 SEF 26 S1 25 S0 24 CB0 23 CB1 22 CB2 21 CB3 20 CB4 19 CB5 18 DB15 17 DB14 16 DB13 15 DB12 Features Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil’ QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) Single Event Upset (SEU) Immunity: <1 x 10 (Typ) Dose Rate Upset . . . . . . . . . . . . . . . . >10 Dose Rate Survivability . . . . . . . . . . . >10 Latch-Up Free Under Any Conditions Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min Input Current ≤ 1µA at VOL, VOH Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ) 11 12 -10 Errors/Bit/Day SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg RAD (Si)/s, 20ns Pulse RAD (Si)/s, 20ns Pulse DB7 9 DB8 10 DB9 11 DB10 12 DB11 13 GND 14 Description The Intersil ACS630MS is a Radiation Hardened 16-bit parallel...