AD6620

a FEATURES High Input Sample Rate 65 MSPS Single Channel Real 32.5 MSPS Diversity Channel Real 32.5 MSPS Single Channel Complex NCO Frequency Translation Worst Spur Better than –100 dBc Tuning Resolution Better than 0.02 Hz 2nd Order Cascaded Integrator Comb FIR Filter Linear Phase, Fixed Coefficients Programmable Decimation Rates: 2, 3 . . . 16 5th Order Cascaded Integrator Comb FIR Filter Linear Phase, Fixed Coefficients Programmable Decimation Rates: 1, 2, 3 . . . 32 Programmable Decimating RAM Coefficient FIR Filter Up to 130 Million Taps per Second 256 20-Bit Programmable Coefficients Programmable Decimation Rates: 1, 2, 3 . . . 32 Bidirectional Synchronization Circuitry Phase Aligns NCOs Synchronizes Data Output Clocks Serial or Parallel Baseband Outputs Pin Selectable Serial or Parallel Serial Works with SHARC, ADSP-21xx, Most Other DSPs 16-Bit Parallel Port, Interleaved I and Q Outputs Two Separate Control and Configuration Ports Generic ␮ P Port, Serial Port 3.3 V Optimized CMOS Process JTAG Boundary Scan GENERAL DESCRIPTION REAL, DUAL REAL, OR COMPLEX INPUTS 65 MSPS Digital Receive Signal Processor AD6620 FUNCTIONAL BLOCK DIAGRAM I CIC FILTERS I FIR FILTER I OUTPUT FORMAT SERIAL OR PARALLEL OUTPUTS Q COS –SIN Q Q COMPLEX NCO EXTERNAL SYNC CIRCUITRY JTAG PORT ␮P OR SERIAL CONTROL both narrowband and wideband carriers to be extracted. The RAM-based architecture allows easy reconfiguration for multimode applications. The decimating filters remove unwanted sign...