DatasheetsPDF.com

AD9222 Datasheet

Data Sheet FEATURES 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock o.

Analog Devices
AD9222.pdf

Preview

Preview
Preview

Analog Devices AD9222 Datasheet
Data Sheet FEATURES 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold cir.






Data Sheet FEATURES 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock o.

Analog Devices
AD9222.pdf

Preview

Preview
Preview

Analog Devices AD9222 Datasheet
Data Sheet FEATURES 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold cir.






40/50 MSPS Serial LVDS 1.8 V A/D Converter

Data Sheet FEATURES 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold cir.


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)