14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9258
08124-001
FEATURES
SNR = 77.6 d...
14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9258
08124-001
FEATURES
SNR = 77.6 dBFS @ 70 MHz and 125 MSPS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V
CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz −152.8 dBm/Hz small signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS Optional on-chip dither Programmable internal ADC
voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes
APPLICATIONS
Communications Diversity radio systems Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO/ SCLK/ DCS DFS CSB
DRVDD
AD9258
SPI
VIN+A VIN–A
ADC
PROGRAMMING DATA
CMOS/LVDS 14 OUTPUT BUFFER
ORA
D13A (MSB) TO D0A (LSB)
VREF SENSE
VCM RBIAS VIN–B VIN+B
REF SELECT
ADC MULTICHIP
SYNC
DIVIDE 1 TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
CMOS/LVDS 14 OUTPUT BUFFER
CLK+ CLK–
DCOA DCOB
ORB D13B (MSB) TO D0B (LSB)
AGND SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE
CMOS PI...