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AD9554 Datasheet

Part Number AD9554
Manufacturers Analog Devices
Logo Analog Devices
Description Multiservice Line Card Adaptive Clock Translator
Datasheet AD9554 DatasheetAD9554 Datasheet (PDF)

Data Sheet Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554 FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261 Auto/manual holdover and reference swi.

  AD9554   AD9554






Part Number AD9559
Manufacturers Analog Devices
Logo Analog Devices
Description Multiservice Line Card Adaptive Clock Translator
Datasheet AD9554 DatasheetAD9559 Datasheet (PDF)

Data Sheet Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9559 FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover Adaptive c.

  AD9554   AD9554







Part Number AD9558
Manufacturers Analog Devices
Logo Analog Devices
Description Quad Input Multiservice Line Card Adaptive Clock Translator
Datasheet AD9554 DatasheetAD9558 Datasheet (PDF)

Data Sheet Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync AD9558 FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover 4 ref.

  AD9554   AD9554







Part Number AD9557
Manufacturers Analog Devices
Logo Analog Devices
Description Dual Input Multiservice Line Card Adaptive Clock Translator
Datasheet AD9554 DatasheetAD9557 Datasheet (PDF)

Data Sheet Dual Input Multiservice Line Card Adaptive Clock Translator AD9557 FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover 2 reference inputs (s.

  AD9554   AD9554







Part Number AD9554-1
Manufacturers Analog Devices
Logo Analog Devices
Description Multiservice Line Card Adaptive Clock Translator
Datasheet AD9554 DatasheetAD9554-1 Datasheet (PDF)

Data Sheet Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554-1 FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261 Auto/manual holdover and reference s.

  AD9554   AD9554







Multiservice Line Card Adaptive Clock Translator

Data Sheet Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554 FEATURES Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261 Auto/manual holdover and reference switchover Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications Quad digital phase-locked loop (DPLL) architecture with four reference inputs (single-ended or differential) 4 × 4 crosspoint allows any reference input to drive any PLL Input reference frequencies from 2 kHz to 1000 MHz Reference validation and frequency monitoring: 2 ppm Programmable input reference switchover priority 20-bit programmable input reference divider 8 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECLcompatible Output frequency range: 430 kHz to 941 MHz Programmable 18-bit integer and 24-bit fractional feedback divider in digital PLL Programmable loop bandwidths from 0.1 Hz to 4 kHz Optional off-chip EEPROM to store power-up profile 72-lead (10 mm × 10 mm) LFCSP package APPLICATIONS Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport net.


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