AD9576

Data Sheet FEATURES Single, low phase noise, fully integrated VCO/fractional-N PLL core VCO range: 2375 MHz to 2725 MHz Integrated loop filter (requires a single external capacitor) 2 differential, XTAL, or single-ended reference inputs Reference monitoring capability Automatic redundant XTAL switchover Minimal transient, smooth switching Typical RMS jitter <0.3 ps (12 kHz to 20 MHz), integer-N translations <0.5 ps (12 kHz to 20 MHz), fractional-N translations Input frequency 8 kHz, 1.544 MHz, 2.048 MHz, and 10 MHz to 325 MHz Preset frequency translations via pin strapping (PPRx) Using a 25 MHz input reference 24.576 MHz, 25 MHz, 33.33 MHz, 50 MHz, 70.656 MHz, 100 MHz, 125 MHz, 148.5 MHz, 156.25 MHz, 161.1328 MHz, 312.5 MHz, 322.2656 MHz, 625 MHz, or 644.5313 MHz Using a 19.44 MHz input reference 50 MHz, 100 MHz, 125 MHz, 156.25 MHz, 161.1328 MHz, or 644.5313 MHz Using a 30.72 MHz input reference 25 MHz, 50 MHz, 100 MHz, 125 MHz, or 156.25 MHz Single, general-purpose, fully integrated VCO/integer-N PLL core VCO range: 750 MHz to 825 MHz Integrated loop filter Independent, duplicate reference input or operation from the fractional-N PLL active reference input Input frequency: 25 MHz Preset frequency translations via pin strapping (PPRx) 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 100 MHz, 133.33 MHz, 200 MHz, or 400 MHz Up to 3 copies of reference clock output 11 pairs of configurable differential outputs Output drive formats 3 outputs: HSTL, LVDS, HCSL, 1.8 V CMOS, 2.5 V/3.3 V CMO...