AD9628

Data Sheet 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9628 FEATURES 1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SNR = 71.2 dBFS @ 70 MHz SFDR = 93 dBc @ 70 MHz Low power: 101 mW/channel @ 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.25 LSB Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand-held scope meters Portable medical imaging Ultrasound Radar/LIDAR FUNCTIONAL BLOCK DIAGRAM AVDD AGND SDIO SCLK CSB VIN+A VIN–A VREF SENSE VCM RBIAS VIN–B VIN+B REF SELECT SPI ADC PROGRAMMING DATA MUX OPTION AD9628 ADC DIVIDE DUTY CYCLE 1 TO 8 STABILIZER MODE CONTROLS CMOS/LVDS OUTPUT BUFFER CMOS/LVDS OUTPUT BUFFER ORA D11A D0A DCOA DRVDD ORB D11B D0B DCOB CLK+ CLK– SYNC DCS PDWN DFS OEB NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1....